Answer Posted / sudeep

This is cache write hit policy,
1. write through:- The information is written to both the
cache and the main memory upon a hit,
2. write back:- The inforamtion is written to only cache,
the main memory is updated upon a read miss.

Differences between IRSIM and SPICE?

5405

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Explain the working of Insights of an inverter ?

1200

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1556

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2409

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Explain how MOSFET works?

3210

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What is the critical path in a SRAM?

3136

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How to improve these parameters? (Cascode topology, use long channel transistors)

2152

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What is look up table in vlsi?

953

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

2986

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What was your role in the silicon evaluation/product ramp? What tools did you use?

3666

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Tell me how MOSFET works.

2386

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what is multiplexer?

1119

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How logical gates are controlled by boolean logic?

1031

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what is the use of defpararm?

1120

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Implement a 2 I/P and gate using Tran gates?

3985

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