What does the above code synthesize to?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Tell me how MOSFET works.
Why do we need both PMOS and NMOS transistors to implement a pass gate?
what is charge sharing?
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
How does a Bandgap Voltage reference work?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Given a circuit and asked to tell the output voltages of that circuit?
1 Answers Intel, Omega Healthcare,
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
what is the doping?