Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

---

Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

---

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

---

what are three regions of operation of MOSFET and how are they used?

0 Answers  

---

---

What happens if we delay the enabling of Clock signal?

0 Answers  

---

Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

---

Explain what is slack?

0 Answers  

---

Explain various adders and difference between them?

0 Answers   Intel,

---

Explain what is multiplexer?

0 Answers  

---

How logical gates are controlled by boolean logic?

0 Answers  

---

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

---