What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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Explain what is the depletion region?

0 Answers  

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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What is the difference between cmos and bipolar technologies?

0 Answers  

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Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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What are the different classification of the timing control?

0 Answers  

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is the ideal input and output resistance of a current source?

0 Answers  

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