In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?



In what cases do you need to double clock a signal before presenting it to a synchronous state mac..

Answer / sudeep

when ur transfering a data b/w two different clock domains,
ex:- The Fsm and ur outside design is working at different
frequencies, to synchronise these signals u do double
clocking to avoid metastability before transferring it into
the FSM.

Is This Answer Correct ?    8 Yes 0 No

Post New Answer

More VLSI Interview Questions

What is the depletion region?

1 Answers  


Explain how binary number can give a signal or convert into a digital signal?

0 Answers  


For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,


What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,






Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,


Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  


what is verilog?

0 Answers  


Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,


Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

1 Answers   Intel,


Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,


Explain the difference between write through and write back cache.

2 Answers   Intel,


Categories