What is SPICE?

4 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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what is verilog?

0 Answers  

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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what is Latch up?How to avoid Latch up?

3 Answers  

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Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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Explain Clock Skew?

6 Answers   Intel, nvidia,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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What are the various regions of operation of mosfet? How are those regions used?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

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