Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

What is the purpose of having depletion mode device?

0 Answers  


What is the most complicated/valuable program you written in C/C++?

23 Answers   HCL, IBM, Intel, TCS, TVS, Wipro,


Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,


What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,


Mention what are three regions of operation of mosfet and how are they used?

0 Answers  


How to find the read failiure probablity in SRAM?

2 Answers  


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,


Mention what are the different gates where Boolean logic are applicable?

0 Answers  


Differences between functions and Procedures in VHDL?

5 Answers   Intel,


what is Channel length modulation?

2 Answers   Intel,


What are the different design constraints occur in the synthesis phase?

0 Answers  


How can you model a SRAM at RTL Level?

0 Answers   Infosys,


Categories