Explain what is Verilog?

0 Answers  

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why is the number of gate inputs to CMOS gates usually limited to four?

0 Answers  

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How can you model a SRAM at RTL Level?

1 Answers  

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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What is the main function of metastability in vsdl?

0 Answers  

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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What is the critical path in a SRAM?

0 Answers  

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Give various factors on which threshold voltage depends.

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

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