Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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Are you familiar with the term MESI?

1 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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what is the difference between the TTL chips and CMOS chips?

0 Answers  

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Explain the various MOSFET Capacitances & their significance?

1 Answers  

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Explain various adders and difference between them?

0 Answers   Intel,

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Why does the present vlsi circuits use mosfets instead of bjts?

0 Answers  

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Draw the SRAM Write Circuitry

0 Answers   Infosys,

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Design an 8 is to 3 encoder using 4 is to encoder?

0 Answers   Intel,

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What is charge sharing?

2 Answers   Cypress Semiconductor, Intel,

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