Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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6-T XOR gate?

0 Answers   Intel,

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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Explain various adders and diff between them?

1 Answers   Intel,

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How does a Bandgap Voltage reference work?

0 Answers  

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What is the function of chain reordering?

0 Answers  

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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Explain the working of Insights of an inverter ?

0 Answers   Intel,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1 Answers   Intel,

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While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

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what are three regions of operation of MOSFET and how are they used?

0 Answers  

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