Explain what is the depletion region?
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what is Latch up?How to avoid Latch up?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
What is setup time and hold time?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
What are set up time & hold time constraints? What do they signify?
What?s the critical path in a SRAM?
2 Answers Infosys, Intel, Texas,
What is Fermi level?
What are the steps required to solve setup and hold violations in vlsi?
What products have you designed which have entered high volume production?
What are the ways to Optimize the Performance of a Difference Amplifier?
Give the expression for CMOS switching power dissipation?
2 Answers Cypress Semiconductor,