In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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What?s the difference between Testing & Verification?

6 Answers   Infosys,

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What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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Have you studied buses? What types?

1 Answers   Intel,

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What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  

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what is the doping?

5 Answers  

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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