Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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What is LVS, DRC?

10 Answers   IBM, Intel,

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

0 Answers   Intel, Sun Microsystems,

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What is component binding?

2 Answers   Intel,

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Differences between functions and Procedures in VHDL?

5 Answers   Intel,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

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What is polymorphism? (C++)

2 Answers   Intel,

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