How can you model a SRAM at RTL Level?
Why don?t we use just one NMOS or PMOS transistor as a transmission gate?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain what is slack?
What transistor level design tools are you proficient with? What types of designs were they used on?
Mention what are the different gates where Boolean logic are applicable?
Draw a CMOS Inverter. Explain its transfer characteristics
Explain sizing of the inverter?
What is the function of tie-high and tie-low cells?
Give various factors on which threshold voltage depends.
Insights of a 2 input NOR gate. Explain the working?
What is pipelining and how can we increase throughput using pipelining?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?