Explain how Verilog is different to normal programming language?

0 Answers  

---

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

---

How do you detect a sequence of "1101" arriving serially from a signal line?

7 Answers   nvidia,

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

---

---

If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

0 Answers   Intel,

---

How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

---

Explain the various MOSFET Capacitances & their significance ?

1 Answers   Infosys,

---

Implement F= not (AB+CD) using CMOS gates?

0 Answers   Intel,

---

Differences between IRSIM and SPICE?

0 Answers   Intel,

---

Are you familiar with the term MESI?

0 Answers   Intel,

---