What are the different classification of the timing control?
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What are the different measures that are required to achieve the design for better yield?
For CMOS logic, give the various techniques you know to minimize power consumption
What is Body Effect?
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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Are you familiar with VHDL and/or Verilog?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Explain the working of differential sense amplifier?
If not into production, how far did you follow the design and why did not you see it into production?
How does Vbe and Ic change with temperature?
What is the critical path in a SRAM?
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