Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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What is FPGA?

7 Answers   Intel,

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Explain Clock Skew?

6 Answers   Intel, nvidia,

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What is component binding?

2 Answers   Intel,

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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What happens if we delay the enabling of Clock signal?

4 Answers  

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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