Answer Posted / sunil b r
he accumulation of a small positive charge on the source of
a MOS switch which occurs after the switch has been turned
off due to the parasitic capacitance that exists between the
gate and the source of the transistor, known as clock
feedthrough, is reduced by utilizing a split-gate MOS
transistor, and by continuously biasing one of the gates of
the split-gate transistor.
| Is This Answer Correct ? | 25 Yes | 3 No |
Post New Answer View All Answers
Tell me how MOSFET works.
What was your role in the silicon evaluation or product ramp? What tools did you use?
What types of high speed CMOS circuits have you designed?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
What are the different classification of the timing control?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Design an 8 is to 3 encoder using 4 is to encoder?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What are the changes that are provided to meet design power targets?
What is the difference between synchronous and asynchronous reset?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
How can you model a SRAM at RTL Level?
How does a Bandgap Voltage reference work?
What is look up table in vlsi?
What is Body Effect?