What is clock feed through?

Answer Posted / sunil b r

he accumulation of a small positive charge on the source of
a MOS switch which occurs after the switch has been turned
off due to the parasitic capacitance that exists between the
gate and the source of the transistor, known as clock
feedthrough, is reduced by utilizing a split-gate MOS
transistor, and by continuously biasing one of the gates of
the split-gate transistor.

Is This Answer Correct ?    25 Yes 3 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

How can you construct both PMOS and NMOS on a single substrate?

4592


Design an 8 is to 3 encoder using 4 is to encoder?

960


What transistor level design tools are you proficient with? What types of designs were they used on?

2982


What are the different measures that are required to achieve the design for better yield?

689


Explain how Verilog is different to normal programming language?

779






How do you size NMOS and PMOS transistors to increase the threshold voltage?

2649


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

839


Explain Cross section of an NMOS transistor?

656


Implement a 2 I/P and gate using Tran gates?

3609


What was your role in the silicon evaluation/product ramp? What tools did you use?

3333


Implement F= not (AB+CD) using CMOS gates?

3645


What types of high speed CMOS circuits have you designed?

2170


Explain the operation of a 6T-SRAM cell?

4164


Write a program to explain the comparator?

782


What are the changes that are provided to meet design power targets?

745