How do you size NMOS and PMOS transistors to increase the
threshold voltage?
Cross section of an NMOS transistor?
Explain Basic Stuff related to Perl?
Draw a CMOS Inverter. Explain its transfer characteristics
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What is the function of chain reordering?
Mention what are the two types of procedural blocks in Verilog?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
What are the different ways in which antenna violation can be prevented?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Why do we use a Clock tree?
What is the purpose of having depletion mode device?
Are you familiar with the term MESI?