Answer Posted / bhushan

D-Latch is a level sensitive flip-flop.
output changes as long as clock is High(for +ve level
sensitive) or High(for -ve level sensitive)


library ieee;
use ieee.std_logic_1164.all;

entity D_latch is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end D_latch;

architecture arch_D_latch of D_latch is
begin
process(d,clk)
begin
-- +ve level sensitive
if(clk = '1') then
q <= d;
else
q <= q;
end if;
end process;

end arch_D_latch;

What is the difference between synchronous and asynchronous reset?

1097

---

What was your role in the silicon evaluation or product ramp? What tools did you use?

2333

---

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2676

---

Draw the Layout of an Inverter?

2507

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2337

---

What is threshold voltage?

1191

---

If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2505

---

What are the various regions of operation of mosfet? How are those regions used?

1140

---

Explain how MOSFET works?

3242

---

what is the difference between the TTL chips and CMOS chips?

1133

---

How can you model a SRAM at RTL Level?

5737

---

What does it mean “the channel is pinched off”?

1359

---

Describe the various effects of scaling?

4796

---

Explain the working of Insights of a pass gate ?

1239

---

What transistor level design tools are you proficient with? What types of designs were they used on?

5070

---