What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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How does a Bandgap Voltage reference work?

0 Answers  

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Explain the working of Insights of an inverter ?

0 Answers   Intel,

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Id vs. Vds Characteristics of NMOS and PMOS transistors?

1 Answers   Brillient, Intel, ISRO,

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Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

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Give the cross-sectional diagram of the cmos.

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What happens when the gate oxide is very thin?

3 Answers   Intel,

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Are you familiar with the term MESI?

0 Answers   Intel,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Who provides the DRC rules?

5 Answers   Intel,

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