Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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What is the function of tie-high and tie-low cells?

0 Answers  

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Explain about 6-T XOR gate?

0 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What is threshold voltage?

0 Answers  

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What are the different classification of the timing control?

0 Answers  

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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what is body effect?

1 Answers  

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Explain what is slack?

0 Answers  

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