Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
What transistor level design tools are you proficient with? What types of designs were they used on?
Are you familiar with VHDL and/or Verilog?
What is the function of tie-high and tie-low cells?
Implement F= not (AB+CD) using CMOS gates?
Give the various techniques you know to minimize power consumption?
Basic Stuff related to Perl?
What is interrupt latency?
Mention what are the different gates where Boolean logic are applicable?
What transistor level design tools are you proficient with? What types of designs were they used on?
What is validation?