Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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Are you familiar with the term MESI?

0 Answers   Intel,

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What is the difference between the mealy and moore state machine?

0 Answers  

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Explain what is the depletion region?

0 Answers  

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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What is the purpose of having depletion mode device?

0 Answers  

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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