Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Why do we use a Clock tree?

3 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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How does a Bandgap Voltage reference work?

0 Answers  

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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