Explain the Charge Sharing problem while sampling data from a Bus?

0 Answers  

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What is the difference between nmos and pmos technologies?

0 Answers  

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Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

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What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  

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What's the price in 1K quantity?

0 Answers   Wipro,

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If not into production, how far did you follow the design and why did not you see it into production?

0 Answers   Intel,

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What are the different measures that are required to achieve the design for better yield?

0 Answers  

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What is the function of chain reordering?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,

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