In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

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Why do we use a Clock tree?

3 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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Are you familiar with the term snooping?

1 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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Implement F= not (AB+CD) using CMOS gates?

0 Answers   Intel,

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Explain how Verilog is different to normal programming language?

0 Answers  

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  

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Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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