Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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What is the critical path in a SRAM?

0 Answers  

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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Explain Cross section of a PMOS transistor?

0 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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Describe the various effects of scaling?

0 Answers   Infosys,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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Explain Clock Skew?

6 Answers   Intel, nvidia,

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If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1 Answers  

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