Explain what is scr (silicon controlled rectifier)?
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Draw the SRAM Write Circuitry
what is body effect?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
What is the function of chain reordering?
Write a pseudo code for sorting the numbers in an array?
What is the purpose of having depletion mode device?
What are the different design constraints occur in the synthesis phase?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What are set up time & hold time constraints? What do they signify?
Explain what is the use of defpararm?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.