What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is the function of tie-high and tie-low cells?

0 Answers  

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How logical gates are controlled by boolean logic?

0 Answers  

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What is the build-in potential?

1 Answers   Wipro,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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What are the different classification of the timing control?

0 Answers  

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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What is Fermi level?

5 Answers  

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