What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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How do you detect if two 8-bit signals are same?

6 Answers  

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What types of CMOS memories have you designed? What were their size? Speed?

0 Answers   Intel, Wipro,

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What is hot electron effect?

3 Answers   Intel,

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what is Channel length modulation?

2 Answers   Intel,

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Give various factors on which threshold voltage depends.

0 Answers  

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How to improve these parameters? (Cascode topology, use long channel transistors)

0 Answers  

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What is LVS, DRC?

10 Answers   IBM, Intel,

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what is the difference between the TTL chips and CMOS chips?

0 Answers  

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