In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?

Answer Posted / amar

this situation basically arises when a signal does clock
domain crossing. to synchronize the clock with the target
domain clock and to avoid metastability issues synchronizers
which are like double clocking are used in designs

Is This Answer Correct ?    19 Yes 1 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

what is Slack?

802


What does the above code synthesize to?

2133


What's the price in 1K quantity?

2475


what is multiplexer?

759


Draw the SRAM Write Circuitry

780






What are the changes that are provided to meet design power targets?

745


What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2101


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

839


Basic Stuff related to Perl?

2495


For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1046


Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2736


What is the difference between the mealy and moore state machine?

687


what are three regions of operation of MOSFET and how are they used?

798


What are the different gates where boolean logic are applicable?

674


Explain the Charge Sharing problem while sampling data from a Bus?

2223