Interested to Buy Any Domain ? << Click Here >> for more details...
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
- 0 Answers
- 1172 Views
- Infosys, I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
Explain Basic Stuff related to Perl?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Insights of a pass gate. Explain the working?
Are you familiar with the term MESI?
what is a sequential circuit?
What is threshold voltage?
Explain the Working of a 2-stage OPAMP?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Why is OOPS called OOPS? (C++)
What was your role in the silicon evaluation/product ramp? What tools did you use?
86 Family 
