For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

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Explain the Charge Sharing problem while sampling data from a Bus?

0 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What is FPGA?

7 Answers   Intel,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Describe the various effects of scaling?

0 Answers   Infosys,

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What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

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Give the expression for CMOS switching power dissipation?

2 Answers   Cypress Semiconductor,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

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