How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

Question Posted / teja@tez

No Answer is Posted For this Question
Be the First to Post Answer

More VLSI Interview Questions

Describe the various effects of scaling?

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

Explain Cross section of a PMOS transistor?

What?s the difference between Testing & Verification?

Mention what are the two types of procedural blocks in Verilog?

What does it mean “the channel is pinched off”?

Draw a 6-T SRAM Cell and explain the Read and Write operations

What are the different ways in which antenna violation can be prevented?

Explain sizing of the inverter?

Explain the working of 4-bit Up/down Counter?

Explain what is the depletion region?

Cross section of a PMOS transistor?

For more VLSI Interview Questions Click Here