Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What are the main issues associated with multiprocessor
caches and how might you solve them?

Answer Posted / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

Is This Answer Correct ?    10 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Give the cross-sectional diagram of the cmos.

1000


How binary number can give a signal or convert into a digital signal?

1246


What is the difference between cmos and bipolar technologies?

1134


Differences between IRSIM and SPICE?

5439


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1204


Explain how logical gates are controlled by Boolean logic?

1191


Explain the operation of a 6T-SRAM cell?

4513


Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1370


what is the difference between the TTL chips and CMOS chips?

1133


Explain the Working of a 2-stage OPAMP?

1198


What is the difference between nmos and pmos technologies?

1115


How does Vbe and Ic change with temperature?

3518


Explain what is the depletion region?

1088


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1455


why is the number of gate inputs to CMOS gates usually limited to four?

1346