In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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Explain what is Verilog?

0 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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Insights of a 4bit adder/Sub Circuit?

0 Answers   Intel,

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What are the different types of skews used in vlsi?

1 Answers  

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Give the cross-sectional diagram of the cmos.

0 Answers  

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What is look up table in vlsi?

0 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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What is component binding?

2 Answers   Intel,

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What is the depletion region?

1 Answers  

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