What are the main issues associated with multiprocessor
caches and how might you solve them?
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Describe the various effects of scaling?
If not into production, how far did you follow the design and why did not you see it into production?
What is Fermi level?
What is validation?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Tell me how MOSFET works.
Implement an Inverter using a single transistor?
What is setup time and hold time?
Insights of a pass gate. Explain the working?
What is latchup? Explain the methods used to prevent it?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?