Answer Posted / purna
The main goals of CTS are
1. Clock signal is propagate to all flops in same time.
2. Low global and local skew.
3. Less insertion delay.
4. For low power designs Clock gating cells are added based
on the designer requirement.
5.Selecting a tree structure from (H,Y,binary and fish bone
etc...)
6. less number of buffer and inverters in the clock path.
7. Clock pin has high fanout to balance skew, we need to
synthesis the clock path separately.
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