What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Differences between IRSIM and SPICE?

0 Answers   Intel,

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Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is the purpose of having depletion mode device?

0 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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What is the ideal input and output resistance of a current source?

0 Answers  

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What is polymorphism? (C++)

2 Answers   Intel,

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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