Interested to Buy Any Domain ? << Click Here >> for more details...
Process technology? What package was used and how did you
model the package/system? What parasitic effects were
considered?
- 0 Answers
- 2337 Views
- Intel, I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
6-T XOR gate?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
Insights of a 2 input NOR gate. Explain the working?
Explain how MOSFET works?
Id vs. Vds Characteristics of NMOS and PMOS transistors?
1 Answers Brillient, Intel, ISRO,
What types of high speed CMOS circuits have you designed?
How does Vbe and Ic change with temperature?
How can you construct both PMOS and NMOS on a single substrate?
Explain the operation of a 6T-SRAM cell?
86 Family 
