What are set up time & hold time constraints? What do they
signify?
Answer Posted / guest
Setup time: Time before the active clock edge of the
flipflop, the input should be stable. If the signal changes
state during this interval, the output of that flipflop
cann't be predictable (called metastable).
Hold Time: The after the active clock edge of the flipflop,
the input should be stable. If the signal changes during
this interval, the output of that flipflop cann't be
predictable (called metastable).
| Is This Answer Correct ? | 51 Yes | 4 No |
Post New Answer View All Answers
How does Vbe and Ic change with temperature?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What was your role in the silicon evaluation/product ramp? What tools did you use?
what is verilog?
Explain what is the depletion region?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
What is the difference between cmos and bipolar technologies?
What is the function of chain reordering?
Are you familiar with the term snooping?
Give various factors on which threshold voltage depends.
What is the difference between nmos and pmos technologies?
Explain the working of Insights of an inverter ?
Explain the operation considering a two processor computer system with a cache for each processor.
What is the difference between the mealy and moore state machine?
what is multiplexer?