Give the various techniques you know to minimize power
consumption?
- 5 Answers
- 11687 Views
- I also Faced
- E-Mail Answers
Answer Posted / narayanachowdary
clock gating
multiple thresholdvoltages,
logic restructuring,....
| Is This Answer Correct ? | 2 Yes | 0 No |
Post New Answer View All Answers
For CMOS logic, give the various techniques you know to minimize power consumption
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
6-T XOR gate?
What are the Advantages and disadvantages of Mealy and Moore?
What are the steps involved in designing an optimal pad ring?
What is the critical path in a SRAM?
Give the cross-sectional diagram of the cmos.
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Write a program to explain the comparator?
What is the function of tie-high and tie-low cells?
What's the price in 1K quantity?
What are the main issues associated with multiprocessor caches and how might you solve them?
Explain what is scr (silicon controlled rectifier)?
Draw a 6-T SRAM Cell and explain the Read and Write operations
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
