What are the limitations in increasing the power supply to
reduce delay?
Answer Posted / narasimha reddy d l
power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases
| Is This Answer Correct ? | 1 Yes | 2 No |
Post New Answer View All Answers
What is the difference between the mealy and moore state machine?
What does the above code synthesize to?
What is look up table in vlsi?
What is the ideal input and output resistance of a current source?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What are the different ways in which antenna violation can be prevented?
Describe the various effects of scaling?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Explain the working of 4-bit Up/down Counter?
Explain various adders and difference between them?
Write a VLSI program that implements a toll booth controller?
What is the main function of metastability in vsdl?
Explain about 6-T XOR gate?
Design an 8 is to 3 encoder using 4 is to encoder?
What is threshold voltage?