Answer / suresh

clock skew,positive skew,negative skew

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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Explain CMOS Inverter transfer characteristics?

0 Answers   ADS,

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Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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what is Latch up?How to avoid Latch up?

3 Answers  

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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What is SPICE?

4 Answers   Intel,

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What is validation?

2 Answers   Intel,

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If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1 Answers   Intel,

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Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1 Answers   Intel,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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