How logical gates are controlled by boolean logic?
Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?
What are the main issues associated with multiprocessor caches and how might you solve them?
What is the ideal input and output resistance of a current source?
Cross section of a PMOS transistor?
what is Early effects and their physical origin.
What happens to delay if you increase load capacitance?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
What are the steps required to solve setup and hold violations in vlsi?
Differences between netlist of HSPICE and Spectre?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
What is pipelining and how can we increase throughput using pipelining?