Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

---

What is clock feed through?

2 Answers   Intel,

---

What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

---

If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

---

Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

---

Give the cross-sectional diagram of the cmos.

0 Answers  

---

What is SPICE?

4 Answers   Intel,

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

---

What is look up table in vlsi?

0 Answers  

---

What products have you designed which have entered high volume production?

1 Answers   Intel,

---

If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

---

How can you model a SRAM at RTL Level?

1 Answers  

---