What are the different design constraints occur in the synthesis phase?

0 Answers  

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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what is conductance and valence band?

1 Answers  

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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what is Latch up?How to avoid Latch up?

3 Answers  

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what is the difference between the TTL chips and CMOS chips?

0 Answers  

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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What was your role in the silicon evaluation/product ramp? What tools did you use?

0 Answers   Intel,

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what is SCR (Silicon Controlled Rectifier)?

0 Answers  

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Explain how Verilog is different to normal programming language?

0 Answers  

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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