Interested to Buy Any Domain ? << Click Here >> for more details...
In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?
- 1 Answers
- 5436 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sudeep
when ur transfering a data b/w two different clock domains,
ex:- The Fsm and ur outside design is working at different
frequencies, to synchronise these signals u do double
clocking to avoid metastability before transferring it into
the FSM.
| Is This Answer Correct ? | 8 Yes | 0 No |
Post New Answer View All Answers
What is the difference between nmos and pmos technologies?
Explain how MOSFET works?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
What are the different design constraints occur in the synthesis phase?
what is Slack?
What types of high speed CMOS circuits have you designed?
Why does the present vlsi circuits use mosfets instead of bjts?
what is verilog?
What is the function of chain reordering?
What are the changes that are provided to meet design power targets?
What transistor level design tools are you proficient with? What types of designs were they used on?
How does a Bandgap Voltage reference work?
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
What are the different ways in which antenna violation can be prevented?
