Answer / suresh ambati

when J and K are 1 output is complementing. Assume clock
period is 10ns and path delay is 2ns .That means for every
2ns output is changing when clock is active.In j k latch
clock pulse is high for 5ns in this case.Assume present
state Qn = 0 .for the first 2ns next state Qn+1 = 1 , and
for the next 2ns i.e at 4ns next state Qn+1 = 0 for the same
clock.Output is not stable for single clock period.This is
race around condition.This is eliminated by master slave jk
flip flop.

Answer / sparsh

RACE AROUND CONDITION IS THAT CONDITION WHEN WE GIVE THE
HIGH INPUTS BOTH TO J AND K IN J-K FLIP FLOP THEN THE
OUTPUT (we can't tell wht will be the
o/p after the time of clk pulse.)START TOGGELING AND DOES
NOT STOP MEANS IT CHANGES 0 TO 1
AND 1 TO 0 RAPIDLY.
WE CAN REMOVE THIS PROBLEM BY USING MASTER SLAVE J-K FLIP
FLOP

Answer / harpreet

WELL...ALL ARE WRITE..AS PER ME RACE AROUND CONDITION
OCCURS WHEN BOTH J AND K INPUTS ARE HIGH..AND THIS PROBLEM
CAN BE ELIMINATED BY USIN MASTER SLAVE JK FLIP FLOP.

Answer / majed

answer 8th is the perfect one, there are two ways to
eliminate race condition, one is by using edge triggering
to flip flop and second by using master slave flip flop,

Answer / rahul

Race around condition occurs in flipflops. When both the
inputs are high, output results in ambiguity. This occurs
due to tp>>delta t, where tp is pulse width and delta t is
propagation delay.
More over it occurs only in level triggered
flipflops and does not occur in edge triggered flipflops.

It can be avoided by making delta t>>tp. Master slave
j-k flipflop uses the same principle and multiple toggling
doesnot occur.

Answer / sunit

This is a condition that occurs when both j and k inputs are
1.Usually we require to have an output that can be
determined but in this case the output is simply
undetermined.In one complete clock cycle the output toggles
many no of times (called as racing) and finally reaches at
an undetermined state.This can be avoided by using two methods
1.By using a clock pulse whose time period is less than the
propagation delay (the time taken to process the output).
2.By making sure that output is toggled after every clock
cycle (this is done by using Master-Slave JK flip flop).

Answer / rupa

In JK flipflop if both the inputs are high,then the output
q and qbar toggles for each clock .to rectify it keep clock
duration less than the propagation delay.

Answer / pradeep

The "Race Around Condition" occurs when J+K=1 i.e. When the
FF is in the toggle mode.
the race around condition in JK latch can be avoided by:
a) Using the edge triggered JK flip flop.
b) Using the master slave JK flip flop.

Answer / vinutha ns

When the inputs of J-K flip flop ie., j=k=1 and the previous state is also 1 then the output of this particular condition is not stable it keeps on toggling from 0 to 1 and from 1 to 0.
this is called race around condition...

it can be overcome by a J-K master slave flipflop......

Answer / alok shrivastava

if j=k=1 and Q=0 and after interval t output Q becomes zero
to one when we applied clock pulse with width t'.
then Q=1 and if j=k=1 then after another interval of t'
output will change .so output will oscillate back and forth
many times in clock interval..it is ambiguous .it is called
race aruond condition.it can be remove by master slave
flipflop or keep t>t'

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