What is Race-around problem? How can you rectify it?
Answers were Sorted based on User's Feedback
Answer / radhar
in jk flip flop race around problem will accur when both
the inputs are high. it can be prevented by using
master slave jk flip flop
Is This Answer Correct ? | 386 Yes | 64 No |
Answer / divya nair
RACE AROUND CONDITION OCCURS WHWN BOTH THE INPUT ARE HIGH
AND THE OUTPUT THUS UNDERGOES A TRANSITION STATE.FOR EXAMPLE
CONSIDER THE INPUT VALUES IN A JK FLIP FLOP;ie;J=K=1 ,THE
OUTPUT Q0=0 IN NORMAL CASE WILL CHANGE TO 1 AND VICE VERSA.
THE REMEDY FOR RACE AROUND PROBLEM CAN BE ELIMINATED BY
USING A MASTER SLAVE J-K FLIP FLOP'S.
Is This Answer Correct ? | 203 Yes | 35 No |
Answer / naveen
RACE AROUND CONDITION IS THAT CONDITION WHEN WE GIVE THE
HIGH INPUTS BOTH TO J AND K IN J-K FLIP FLOP THEN THE OUTPUT
START TOGGELING AND DOES NOT STOP MEANS IT CHANGES 0 TO 1
AND 1 TO 0 RAPIDLY.
WE CAN REMOVE THIS PROBLEM BY USING MASTER SLAVE J-K FLIP FLOP
Is This Answer Correct ? | 151 Yes | 26 No |
Answer / puneet
race around cndition:
it is a problem takes place in j-k ff whn i/ps are high.i.e 1
so whn all i/ps are high thn we can't tell wht will be the
o/p after the time of clk pulse.The time delay in clk pulse
is due to the feed back mechanism .(the o/p is feeded back
to i/p)
this problem can be avoided if delta t >tp .. bt this is nt
possible in real life...
so we can rectify this problem by using master-slave ff
where on e j-k ff act as a master & other act as a slave..
Is This Answer Correct ? | 116 Yes | 17 No |
Answer / megha
A condition in logic network in which the difference in
propagation times through two or more signal paths in the
network can produce an erroneous output.
Is This Answer Correct ? | 137 Yes | 69 No |
Answer / anil kumar
when the both the inputs of j.k. f.f. are high then toggling
condition occur i.e. output changes 0to1 and 1to 0 because
delay in clock . by this the output of Q become uncertain at
the end of clock pulse this is called race around condition
THIS CAN BE REMOVE BY USING MASTER SLAVE
Is This Answer Correct ? | 60 Yes | 9 No |
Answer / ahsin
When both the inputs of J ,K is high then its output
starts to toggle.ie its output will be arbitary ,so to
avoid this problem JK master slave is used to get
desirable propagation delay for toggling.
Is This Answer Correct ? | 52 Yes | 23 No |
A race condition is an undesirable situation that occurs
when a device or system attempts to perform two or more
operations at the same time, but because of the nature of
the device or system, the operations must be done in the
proper sequence in order to be done correctly.
In computer memory or storage, a race condition may occur
if commands to read and write a large amount of data are
received at almost the same instant, and the machine
attempts to overwrite some or all of the old data while
that old data is still being read. The result may be one or
more of the following: a computer crash, an "illegal
operation," notification and shutdown of the program,
errors reading the old data, or errors writing the new
data. This can be prevented by serialization of memory or
storage access, such that if read and write commands are
received close together, the read command is executed and
completed first, by default.
In a network, a race condition may occur if two users
attempt to access an available channel at the same instant,
and neither computer receives notification that the channel
is occupied before the system grants access. Statistically,
this sort of coincidence is most likely to occur in
networks having long lag times, such as those that use
geostationary satellites. To prevent such a race condition
from developing, a priority scheme must be devised. For
example, the subscriber whose username begins with the
earlier letter of the alphabet (or the lower numeral) may
get priority by default when two subscribers attempt to
access the system within a prescribed increment of time.
Hackers can take advantage of race-condition
vulnerabilities to gain unauthorized access to networks.
Race conditions occasionally occur in logic gates when
certain inputs come into conflict. Because the gate output
state takes a finite, nonzero amount of time to react to
any change in input states, sensitive circuits or devices
following the gate may be fooled by the state of the
output, and thereby caused to not operate properly.
Is This Answer Correct ? | 37 Yes | 12 No |
Answer / sibani mohapatra.
when jk flipflop input is both 1,i.e.j=k=1,then race around
problem occur.it can be rectified by using master slave jk
flipflop.
Is This Answer Correct ? | 37 Yes | 20 No |
Answer / ishwar
Let us consider the example of a Flip Flop(or a binary),
because that's the only place I know where Race Around is
observed...
Let us consider a JK Flip Flop (Hereby called FF). The
excitation table of this FF is as follows :
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn Bar ~ Complement of Qn
Let us say that a clock of certain frequency is fed to the
FF, and consider the case of J=K=1, and the propagation
delay of FF is very very less than the clock pulse time
Then the FF continues complementing the output an
unpredictable number of times, thus leading to anomaly in
the final output after the pulse time of the clock is
completed
we can rectify this problem by using master-slave ff
where one j-k ff act as a master & other act as a slave.
Is This Answer Correct ? | 15 Yes | 2 No |
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