Answer Posted / sunit

This is a condition that occurs when both j and k inputs are
1.Usually we require to have an output that can be
determined but in this case the output is simply
undetermined.In one complete clock cycle the output toggles
many no of times (called as racing) and finally reaches at
an undetermined state.This can be avoided by using two methods
1.By using a clock pulse whose time period is less than the
propagation delay (the time taken to process the output).
2.By making sure that output is toggled after every clock
cycle (this is done by using Master-Slave JK flip flop).

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