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There are 2 Flip_Flop with logic between them. Given Clock to Q delay, logic prop. delay, set up and hold times specify maximum clock frequency of system. What happens if second output fed back to first input. Any changes? What happens with timing if second output is fed back to logic between the flops? Good Luck!
1 7634I am shobana from Chennai. I am having my personal interview on 19th Dec at Chennai.kindly mail me the questions to mail id shobana.shanthi@gmail.com
2338Hi, I'm going to attend BHEL interview for exexutive trainee (ET ) on 22nd DEC . Till now if anyone attended the interview pls help me out regarding the interview. I'm an electrical engineer
Bhel,
3 9715hello!my name is sheikh iam preparing for indian engineering servieces,please send me the old question papers..to sheikhshaazforjobs@gmail.com
2039What is ZCT? it operating principle and how is work with RCCB (residual current circuit breaker)?
4 51228In what circumstanced the CT used for protection relay will be saturated?and what will happen to the relay is the CT is saturated?
3 7744Explain the working principle of servomotor
ABB, Bhel, FANUC, GE, Jindal Steel and Power, L&T, SIA, Steelco Gujarat Ltd,
20 54702Post New Electrical Engineering Questions
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hello everybody. what does an abnormal stator winding impedance or dc resistance show? thanx
