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86 Family (470) - VLSI (297)
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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
2838In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
1 5523You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
2674What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
2887What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
2437Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
2329What transistor level design tools are you proficient with? What types of designs were they used on?
3445
what is dsp?
How to control and timing circuitry of the 8085.
How does combination of functions reduce memory requirements in embedded systems?
What are the different ways in which antenna violation can be prevented?
What is a 'volatile' variable?
What is the main function of multiplexed address/data bus?
What is the need for an infinite loop in embedded systems?
You've just been assigned to a project in a new technology how would you get started?
Explain the Various steps in Synthesis?
What are the different types of customizations that is used with the “volatile” keyword?
You have two computers, and you want to get data from one to the other. How could you do it?
How does the interrupt architecture works?
Suppose you buy some rtos, what are the features you look for in?
Tell me what are buses used for communication in embedded system?
This program is in verilog and need help to get it working correctly. This is the code i have so far. Please help. Simple testbench would be great. Thanks\ 'define vend_a_drink {D,dispense,collect} = {IDLE,2'b11}; module drink_machine(nickel_in, dime_in, quarter_in, collect, nickel_out, dime_out, dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q always @ ( nickel_in or dime_in or quarter_in or reset ) begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE; FIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY; TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) 'vend_a_drink; TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) 'vend_a_drink; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; dime_out = 1; end FIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; end THIRTY: if (nickel_in) 'vend_a_drink; else if (dime_in) begin 'vend_a_drink; nickel_out = 1; end else if (quarter_in) begin 'vend_a_drink; dime_out = 1; D = OWE_DIME; end TWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin 'vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase end end always @ (posedge clk ) begin Q = D; end endmodule
