86 Family (470)
VLSI (297)
DSP (55)
Embedded Systems AllOther (399) If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
1379In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1582What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
1517
What's your experience with qa engineering?
Can a pointer be volatile ?
How might a task-based model differ from a threaded model?
What are the temporary registers of 8085?
What products have you designed which have entered high volume production?
How can the signals of the 8086 be categorised?
Tell me how MOSFET works.
Why cannot arrays be passed by values to functions?
Why is the address bus in the 8085 tri-stated and unidirectional?
What is risc architecture?
What is the difference between harvard architecture and von neumann architecture?
What do you do when you get stuck with a problem you can't solve?
Basic Stuff related to Perl?
Tell me what type of scheduling is there in rtos?
Discuss the differences between mocks and stubs/fakes and where you might use them (answers aren't that important here, just the discussion that would ensue).