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86 Family (470) - VLSI (297)
- DSP (55)
- Embedded Systems AllOther (399)
If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
1317In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1530What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
1464
Describe the non-vectored interrupt process?
List some analog modulation techniques.
The address capability of 8085 is 64 kb.explain?
What is the difference between 8085 microprocessor and a 8086 microprocessor?
Explain the differences between stateless and stateful systems, and impacts of state on parallelism.
What is yagni? Is this list of questions an example?
Explain the purpose of the status register?
what are three regions of operation of MOSFET and how are they used?
Tell me can include files be nested?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Device density on a microprocessor/chip?
What is difference between binary semaphore and mutex?
What is the main function of multiplexed address/data bus?
What are the different design constraints occur in the synthesis phase?
Why do we need virtual device drivers when we have physical device drivers?
