If a1M1× DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.
CDAC,
1081In which T-state does the CPU sends the address o memory or I/O and the ALE signal for Demultiplexing
CDAC,
1303What number of the times the instruction sequence below will loop before coming out of loop is MOV AL, 00hA1: INC AL JNZ A1
CDAC,
1251
Explain the difference between mutexes vs semaphores?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
How is EPROM generally erased
How can signals be classified for the 8085 microprocessor?
Explain transmission gate-based d-latch?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Explain the difference between "set" logic, and "procedural" logic.
How can the signals of the 8086 be categorised?
How do you identify hardware errors?
Describe the life-cycle of a software development (application design) process.
Point out the differences between the 8086 and 8088 microprocessor?
What are the different ways in which antenna violation can be prevented?
Mention the types of interrupts that 8085 supports?
Write a VLSI program that implements a toll booth controller?
What is baud rate?
