Answer / baisakhi khasnabis

we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.

Answer / anshuman kumar chanchal

when we put j=1 and k=1 in j-k flip flop, the output, Q
toggles to 0 and 1 continuously; and it becomes uncertain
to predict the output. This condition is known as Race
around condition.
It can be rectified using Master-Slave flip flop.

Answer / sahil gupta

in simple jk flip flor circuit
at condition
j=1 and k=1
every time output toggle w.r.t previous output,we use
single clock in this case so that condition known as race
around condition.by using master slave jk flip flop we can
remove this problem.

Answer / sowmya

A fliplflop is a basic digital memory circuit.In JK
flipflop when the clock pulse is equal to 1 and also when
j=k=1 , we know that the next state is complement of the
present state.but at that instance if clock pulse is
still '1'(high)the o/p again complements.and it repeats
untill clk puls goes back to '0'.this is race aroud conditn.

This is because that clk puls duratn is more than the
propagatn delay of flipflop.to avoid this we need to adjust
the clk pulse duratn or we need to put restriction on clk
pulse width as
clk pls (t)<propgatn delay using mater slave configuratn

Answer / abhinandan kumar

we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
so this can be avoided by using only edgetriggerd ff
rahter than using level triggerd.

Answer / nidhi , b.tech 2nd year ,r.v.s

In a JK flip flop when J=1 and K=1 and clock is applied, the
outputs keep on toggling at every delay time of the flip
flop as long as the clock is present.Hence the output at the
end of the clock pulse is ambiguous.This condition is called
race around condition.

Answer / neeraj kumar

simple jk flip flor circuit
at condition
j=1 and k=1
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.

Answer / ajay yadav

when we put j=1 and k=1 in j-k flip flop, the output, Q
toggles to 0 and 1 continuously; and it becomes uncertain
to predict the output. This condition is known as Race
around condition.
It can be rectified using Master-Slave flip flop.

Answer / divakar mani tripathi

In a J.K(jack kilby) flip flop when we put a condition I.e j=k=1
Then the output of the f.f starts giving response and changes its
value from 0 to 1 and viceversa by the factor of propagation delay
which is equal to the time take by the input to propagate through two NAND gates .As we known the propagation delay of a NAND state is much smaller compared to a general clock pulse time period .So during single clock period output changes many times uncertainly termed as RACING and the signal o/p is termed as racing signal.

To avoid this there are two ways..
1.To make clock period smaller than propagation delay which is much difficult to implement.
2.By having a MASTER SLAVEconfiguration(I.e by having two jk f.f having the inversion of master clock to the slave clock )by which when the master clock is high then the save clock is low by their alternative working we get the response in a whole period and then changes only in other period this is called TOGGLING which can be used furthur....THANKS

Answer / ravi pandey b.tech. a.i.t.s.h

it is timing problem,caused because in the time of tiggering
clock pulse stays in a high state for along time as compare
to propagation delay.

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