Give a circuit to divide frequency of clock cycle by two ?
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Answer / sravan
take a D Flip Flop. when it is reset output(Q) is zero.
connect the clock which u want to divide to the CP input of
FF. connect Q bar (which is one after the reset)to the D
input of Flip Flop. Take the output from the Q pin of the
Flip Flop, which is divided by two
Is This Answer Correct ? | 26 Yes | 3 No |
Answer / priyanka kokil
any single flip flop itself is a freqency divider circuit
Is This Answer Correct ? | 14 Yes | 14 No |
Answer / harikrishna h
take an xor gate, connect output to one of the input of xor gate and other input as the clock. verilog code for the same is given below
module a(input in,rst,output reg ot);
always @(in or rst)
begin
if(rst)
ot<=0;
else
ot<=ot ^ in;
end
endmodule
Is This Answer Correct ? | 0 Yes | 2 No |
Answer / manish sharma
Divide the clock frequency by 2
A 2:1 MUX with CLK as select signal. The 0 select input is just the output. The 1 select input is output_bar(NOT output).
Is This Answer Correct ? | 1 Yes | 4 No |
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